VHDL OF FULL ADDER WITH ISE PROJECT NAVIGATOR (P.49d)

- February 19, 2018

EXPERIMENT NO: 4(B)

Date: 13-02-2018

AIM: TO DESIGN A FULL ADDER.

THEORY:

Full adder is developed to overcome the drawback of Half Adder circuit. It can add two one-bit numbers A and B, and carry c. The full adder is a three input and two output combinational circuit.

VHDL CODE:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity full_adder1 is

Port ( a : in STD_LOGIC;

b : in STD_LOGIC;

cin : in STD_LOGIC;

s : out STD_LOGIC;

c : out STD_LOGIC);

end full_adder1;

architecture Behavioral of full_adder1 is

begin

s<= a xor b xor cin;

c<= (a and b) or (a and cin) or (b and cin);

end Behavioral;

PROCEDURE:

1. Open a new project from the drop down menu by clicking on FILE given on the top left of the screen.

2. Create a new project and name it.

Click on next to enter device properties.
Select the appropriate properties.
Click on next button to enter the new source.
Here select VHDL MODULE.
Give the file name.
Click on next button and enter the ENTITY name.
Select the define module.
Select the ports as input or output and name them.
Click on net and then to on finish.
Write the code for the project under the library entity.
Save the program.
Select the behavioral simulation option from the three modeling options.
Now select the syntax check.
If syntax check comes out to be correct, then proceed further, otherwise check for errors.
Now select synthesize option and go through RTL schematic and view the figure.
Similarly view technology schematic with clicking this option inside synthesize.