VHDL code for half subtractor and full subtractor using ISE project navigator
EXPERIMENT NO: 5(A) Date: 20-02-2018 AIM: TO DESIGN A HALF SUBTRACTOR. THEORY: A half subtractor is a logical circuit that performs a subtraction operation on two binary digits. The half subtractor produces a sum and a borrow bit for the next stage. VHDL CODE: library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity half_subtractor is Port ( a : in STD_LOGIC; b : in STD_LOGIC; d : out STD_LOGIC; bo : out STD_LOGIC); end half_subtractor; architecture Behavioral of half_subtractor is begin d<= a xor b; bo<=(not a) and b; end Behavioral; PROCEDURE: Open a new project from the drop down menu by c