Very Large Scale Integration (VLSI) Technology

EXPERIMENT NO: 4(B) Date: 13-02-2018 AIM: TO DESIGN A FULL ADDER. THEORY: Full adder is developed to overcome the drawback of Half Adder circuit. It can add two one-bit numbers A and B, and carry c. The full adder is a three input and two output combinational circuit. VHDL CODE: library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity full_adder1 is     Port ( a : in  STD_LOGIC;            b : in  STD_LOGIC;            cin : in  STD_LOGIC;            s : out  STD_LOGIC;            c : out  STD_LOGIC); end full_adder1; architecture Behavioral of full_adder1 is begin s<= a xor b xor cin; c<= (a and b) or (a and cin) or (b and cin); end B

EXPERIMENT NO: 4(A) Date: 13-02-2018 AIM: TO DESIGN A HALF ADDER. THEORY: Half adder is a combinational logic circuit with two inputs and two outputs. The half adder circuit is designed to add two single bit binary number A and B. It is the basic building block for addition of two  single bit numbers. This circuit has two outputs carry and sum where carry is denoted by ‘C’ and sum is denoted by ‘S’. VHDL CODE: library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity half_adder1 is     Port ( a : in  STD_LOGIC;            b : in  STD_LOGIC;            s : out  STD_LOGIC;            c : out  STD_LOGIC); end half_adder1; architecture Behavioral of half_adder